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Carbon nanotubes

Over the past few years, IBM has poured a great deal of time and attempt into researching carbon nanotubes (CNTs). The beingness of single-walled carbon nanotubes and their marvelous semiconductor properties occurred independently at both NEC and IBM, and Large Blue has been interested in capitalizing on that discovery for well over a decade. IBM researchers have at present published a paper in which they claim to take demonstrated highly beneficial scaling capabilities in carbon nanotubes.

We've discussed the difficulties of scaling semiconductors every bit the distance between features shrinks with every passing generation, just the specific breakthrough IBM is claiming is in an area of chip design nosotros haven't discussed much. In conventional silicon (or conventional carbon nanotubes, for that matter), there's been a known problem — as semiconductors continue to compress, the contact area between the metallic and semiconductor hasn't been scaling. Generally speaking, smaller contact areas lead to increased resistance, and increased resistance means college heat. Manufacturers have fought back against these trends with a variety of methods, merely the lack of contact scaling is one of the fundamental barriers to pushing silicon to e'er-smaller sizes.

Carbon nanotubes

Paradigm by IBM Research

IBM thinks its carbon nanotube engineering science could solve that trouble. EETimes has an fantabulous write-up of the technology, though information technology hilariously refers to EUV lithography as "already in place," — a announcement that I'thou certain would surprise both Intel and TSMC. With our recent quantum, "Shu-Jen Han, IBM director of nanoscale science and engineering at its T.J. Watson Inquiry Middle (Yorktown, Heights) told EE Times, "nosotros now know how to scale [the contact] and then it is no longer the limiting cistron for carbon nanotube transistors. Our new contacts are measured in angstroms and take just 36 k-ohms of resistance, including both ends."

The new approach involves welding — nanowelding — a nanotube with molybdenum before they are self-aligned as transistor channels. The last step is to rut the assembly to 850C, melting the molybdenum off and creating carbide. Co-ordinate to Richard Doherty, of Envision Engineering, this solution gives IBM a unique reward in scaling all the way downwards to one.8nm. According to EETimes, IBM may exist prepping this technology to be ready at the 5nm node, for introduction at 3nm and below. With the method already proven in theory at 9nm, there seems to be niggling bulwark to further scaling.

A nanotube future?

At that place are, nonetheless, some pointed caveats to these findings. First, there's the fact that IBM is simply currently capable of building p-type transistors using this method. That doesn't hateful that the applied science is useless — many of the proposed most-term solutions for improved silicon scaling rely on dissimilar materials for the p-channel and n-channel, but information technology definitely introduces additional complexity.

The International Technical Roadmap for Semiconductors hasn't issued new reports since 2022; the group is currently evaluating changes to its measuring criteria and formulating new reports, just the 2022 information gear up is still online. Looking back at information technology, the roadmap for most-term introduction of carbon nanotubes wasn't very rosy.

CNTs

This nautical chart shows the suitability of new materials compared to current methods, also as the dates at which they might exist introduced. Carbon nanotubes scored particularly badly in property control, contact viarability, and control of germination, location, and direction. IBM has claimed to have made substantial advances in all three areas since this written report was written. In a 2022 discussion with The Register, IBM Researcher'due south director of Physical Science, Supratik Guha stated: "You have to brand carbon nanotubes with purity levels that are six nines. Today we are at four nines and over a twelvemonth ago [nosotros were] at 98.5 percent." This aligns with the values listed in the 2022 ITRS reports, which were far too low to use for semiconductor manufacturing. IBM is pouring billions into researching CNTs, including each of these bug.

Keeping in mind that each boosted "9" means a full order of magnitude improvement, CNTs still had a very long style to go in 2022. Solving the contact problem, nonetheless, would clear a substantial hurdle, possibly allowing for long-term adoption. If the goal is to bring the engineering in at the 3nm node, there's plenty of time to await — while multiple sources that wrote upward this story skipped this minor point, this prediction is a long fourth dimension out. With nodes at present shifting roughly every 30 months, nosotros're ii years from 10nm and 5 years from 5nm. That puts the introduction of CNTs at the 3nm node, ~2023.